In testing CMOS devices, the measurement of quiescent currents presents several problems. One problem is the length of test time required to measure the quiescent current (IDDQ) of the power pin (VDD) for all the logic states of the CMOS device. Another problem is the long settling time associated with charging bypass-capacitance when low current ranges are used to measure leakage currents at the inputs of device under test (DUT).
The IDD quiescent current (IDDQ) of CMOS devices is measured at different logic states to determine if internal gates of the DUT have excessive leakage. Burn-in data has shown that gates with excessive leakage indicate potential reliability problems. IDDQ measurements are used to detect CMOS devices that will have premature failures.
A CMOS DUT requires a high current (50ma to 1A) during transients between logic states, but the CMOS device only requires a low current (10ua to 100ua) in a static or quiescent condition. A by-pass capacitor is also required to hold the VDD voltage stable during the high current transients between logic states.
To measure the IDDQ of a DUT. The device power supply (DPS) must be capable of rapidly switching from a high current range to a low current range and measure to 1% accuracy. Conventional DPS's take from 5ms to 100ms depending on the by-pass capacitor selected. Conventional methods of switching the current ranges opens or disrupts the voltage and/or current feedback of the DPS. This affects the output voltage of the DPS, which is also the voltage across the by-pass capacitor. The low current range resistor then has to charge the by-pass capacitor back to the programmed voltage. This causes a large time constant due to the current range selected charging the by-pass capacitor. To eliminate this long time constant, a method of switching the current ranges without affecting the output voltage of the DPS is necessary.
Prior methods do not allow the functional test generator to directly control the timing of the current range switching or analog to digital conversion or comparison triggering. Conventional methods use driver and receiver test patterns to control the IDDQ measurements. Special functional test patterns must be written when using a driver and receiver test patterns for IDDQ current range switching measurement timing. To eliminate special test patterns for IDDQ measurement, the IDDQ measurements must be supported by the functional test subsystem.